interrupção+serial+16f628a

[ze]

voce pode fazer:

unsigned char tmp;
tmp=RCREG;tmp=RCREG;

para ver se o buffer está estourando voce pode colocar um led em um pino de porta disponível para monitorar:
P.ex:
RA0=OERR;

veja um trecho do data sheet relacionado a usart (sorry, just english)

"The heart of the receiver is the receive (serial) shift
register (RSR). After sampling the Stop bit, the
received data in the RSR is transferred to the RCREG
register (if it is empty). If the transfer is complete, flag
bit RCIF (PIR1<5>) is set. The actual interrupt can be
enabled/disabled by setting/clearing enable bit RCIE
(PIE1<5>). Flag bit RCIF is a read-only bit, which is
cleared by the hardware. It is cleared when the RCREG
register has been read and is empty. The RCREG is a
double buffered register, (i.e., it is a two deep FIFO). It
is possible for two bytes of data to be received and
transferred to the RCREG FIFO and a third byte begin
shifting to the RSR register. On the detection of the
Stop bit of the third byte, if the RCREG register is still
full then overrun error bit OERR (RCSTA<1>) will be
set. The word in the RSR will be lost. The RCREG
register can be read twice to retrieve the two bytes in
the FIFO. Overrun bit OERR has to be cleared in software.
This is done by resetting the receive logic (CREN
is cleared and then set). If bit OERR is set, transfers
from the RSR register to the RCREG register are inhibited,
so it is essential to clear error bit OERR if it is set.
Framing error bit FERR (RCSTA<2>) is set if a Stop bit
is detected as clear. Bit FERR and the 9th receive bit
are buffered the same way as the receive data. Reading
the RCREG, will load bits RX9D and FERR with
new values, therefore it is essential for the user to read
the RCSTA register before reading RCREG register in
order not to lose the old FERR and RX9D information."